--------------------------------------------------------------------------------
-- Company: Synapse
-- Module Name:    memory - Behavioral
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.VComponents.all;

entity BlockRam is
    Port (
        CLK        : in std_logic;
        RESET      : in std_logic;
        RE         : in std_logic;
        WE         : in std_logic;   
        D          : in std_logic_vector(15 downto 0);
        Q          : out std_logic_vector(15 downto 0);  
        A          : in std_logic_vector(3 downto 0)    
    );              
end BlockRam;

architecture Behavioral of BlockRam is
    
    component RAMB4_S16_S16
    generic( 
        INIT_00 : bit_vector := x"0000000000000000000000000000000000000000000000000000000000000000";
        INIT_01 : bit_vector := x"0000000000000000000000000000000000000000000000000000000000000000";
        INIT_02 : bit_vector := x"0000000000000000000000000000000000000000000000000000000000000000";
        INIT_03 : bit_vector := x"0000000000000000000000000000000000000000000000000000000000000000";
        INIT_04 : bit_vector := x"0000000000000000000000000000000000000000000000000000000000000000";
        INIT_05 : bit_vector := x"0000000000000000000000000000000000000000000000000000000000000000";
        INIT_06 : bit_vector := x"0000000000000000000000000000000000000000000000000000000000000000";
        INIT_07 : bit_vector := x"0000000000000000000000000000000000000000000000000000000000000000";
        INIT_08 : bit_vector := x"0000000000000000000000000000000000000000000000000000000000000000";
        INIT_09 : bit_vector := x"0000000000000000000000000000000000000000000000000000000000000000";
        INIT_0A : bit_vector := x"0000000000000000000000000000000000000000000000000000000000000000";
        INIT_0B : bit_vector := x"0000000000000000000000000000000000000000000000000000000000000000";
        INIT_0C : bit_vector := x"0000000000000000000000000000000000000000000000000000000000000000";
        INIT_0D : bit_vector := x"0000000000000000000000000000000000000000000000000000000000000000";
        INIT_0E : bit_vector := x"0000000000000000000000000000000000000000000000000000000000000000";
        INIT_0F : bit_vector := x"0000000000000000000000000000000000000000000000000000000000000000");
    port ( 
        ADDRA : in    std_logic_vector (7 downto 0); 
        ADDRB : in    std_logic_vector (7 downto 0); 
        CLKA  : in    std_logic; 
        CLKB  : in    std_logic; 
        DIA   : in    std_logic_vector (15 downto 0); 
        DIB   : in    std_logic_vector (15 downto 0); 
        ENA   : in    std_logic; 
        ENB   : in    std_logic; 
        RSTA  : in    std_logic; 
        RSTB  : in    std_logic; 
        WEA   : in    std_logic; 
        WEB   : in    std_logic; 
        DOA   : out   std_logic_vector (15 downto 0); 
        DOB   : out   std_logic_vector (15 downto 0));
    end component;

begin

blockRam : RAMB4_S16_S16
    port map (
        ADDRA(7 downto 4) => "0000",
        ADDRA(3 downto 0) => A,
        CLKA => CLK,
        DIA => D,
        ENA => RE,
        RSTA => RESET,
        WEA => WE,
        DOA => Q,
        ADDRB => "00000000",
        CLKB => clk,
        DIB => "0000000000000000",
        ENB => '0',
        RSTB => '1',
        WEB => '0',
        DOB => open
    );

end Behavioral;
